1. Field of the Invention
This invention relates to a system for checking parity between data transferred between integrated circuit chips while reducing the usage of I/O pins on each of the integrated circuit chips.
2. Description of the Related Art
In computer systems it is desirable to maintain the integrity of data as data is transferred between integrated circuit chips making up the computer system. A common method employed for maintaining data integrity is to provide a parity bit with each group of data bits that are transferred between the integrated circuit chips. Once the data has been received by the receiving integrated circuit chip, parity is checked to ascertain whether an error had occurred during the data transmission.
One limiting factor associated with integrated circuit chips is the number of I/O pins that are available on the chip. A system may require fields of data of different lengths generated on one integrated circuit chip to be transmitted to one or more integrated circuit chips. To maintain data integrity for such transfers, a parity bit is generated for each group of data bits to be transmitted to another given integrated circuit chip and an I/O pin is used to communicate the parity bit. Further, an integrated circuit chip may receive data from more than one integrated circuit chip thereby requiring the use of an I/O pin for each parity bit to be received. Thus, an integrated circuit chip must utilize a number of I/O pins equal to the number of integrated circuit chips to which data is to be sent plus the number of integrated circuit chips from which data is to be received. A conflict arises between the desire to maintain data integrity by providing a parity bit when transferring data between integrated circuit chips and the availability of I/O pins on the integrated circuit chip for receiving and transmitting parity bits to and from other integrated circuit chips.